Method of forming shallow trench isolation

ABSTRACT

A method of forming the shallow trench isolation by introducing a nitrogen treatment after the step of forming the trench is disclosed. The exposed pad oxide layer located on the upper portion of the trench is transferred into silicon oxynitride layer. Therefore, the formation of the bird&#39;s break and electric influence of the device are avoided. Accordingly, the scale down requirement of the future device is also satisfied.

FIELD OF THE INVENTION

The present invention relates to a method of fabricating a semiconductordevice, and more particularly to a method of forming a shallow trenchisolation (STI) by introducing a step of treating an oxide layer bynitrogen after the shallow trench is formed by etching.

BACKGROUND OF THE INVENTION

A completed integrated circuit is generally constructed with thousandsof metal oxide semiconductor (MOS) transistors. In order to avoid acircuit short between neighbored transistors, an isolation structure isemployed for electrical isolating the transistors.

When the circuit integration is increased, size of the electric devicemust be scaled down. Hence, the isolation structure between the devicesalso must be scaled down in accordance with the devices, and therebyresults in a difficult of forming the isolation structure. A variety ofdevice isolation has been developed, wherein a shallow trench isolation(STI) technique is commonly used, and is currently applied in theintegrated circuit process, especially in the sub-half micron integratedcircuit process.

Referring o FIGS. 1 through 5, showing, a conventional process of makingthe shallow trench isolation structure. As shown in FIG. 1, asemiconductor substrate 10, typically a silicon substrate, is provided.A pad oxide layer 12, for example, a silicon oxide layer, is then formedon the semiconductor substrate 10 by heating in an oxygen-containingcondition. After that, a silicon nitride layer 14 is then deposited onthe pad oxide layer 12 by, for example, LPCVD or other depositionmethod. A photolithography process is then performed on the wafer.

Referring to FIG. 2, a layer of photoresist is then patterned to exposethe silicon nitride layer 14 after the forming step of the siliconnitride 14. A predetermined mask pattern is then transferred to thelayer of photoresist to form the photoresist layer 16. Thereafter, anetching process is then performed on the wafer.

Referring to FIG. 3, the formed photoresist layer 16 can be used as themask during the etching process. The underlying silicon nitride layer14, pad oxide layer 12 and substrate 10 are then etched sequentially bywet etching or dry etching. Therefore. a trench 20 is then formed on thesubstrate 10.

Referring to FIG. 4, while the trench 20 has a predetermined depthduring the etching process, a liner oxide layer 18 is then conformalformed on the surface of the etched trench 20. The photoresist layer 16is then removed. Thereafter, a silicon oxide layer 22 is then formed tofill the trench 20 by, for example, CVD or other deposition method. Apolishing process is then preformed on the wafer.

Referring o FIG. 5, a CMP process is then applied to remove the siliconnitride layer 14, oxide layer 22, and pad oxide layer 12, exceed thetrench 20, and leave the layers located within the trench 20. Since thepad oxide layer is exposed, therefore a bird's break is easily formed inthe subsequent processes and the exposed surface of the pad oxide layeris then enlarged, especially in the etching process for patterning theshallow trench.

As described above, a bird's break is easily formed on the pad oxidelayer and the exposed surface of the pad oxide layer is then enlargedduring the etching process for patterning. This bird's break will occupythe active area result in the difficulty to reduce the size of device.

Moreover, although an improved method is applied to inhibit the formingof the bird's break by etching back the pad oxide layer. However, it isdifficult to control the deposition of silicon. Therefore, voids areformed and the electric property of the device is then affected.Accordingly, it is necessary to introduce an effective method to solvethis bird's break problem.

SUMMARY

Since a bird's break is easily formed on the pad oxide layer and theexposed surface of the pad oxide layer is then enlarged during theetching process for patterning in the convention method of forming theshallow trench isolation.

It is therefore one aspect of the present invention to provide a methodof forming a shallow trench isolation. The present invention comprisesthe steps of forming a trench on a substrate, wherein the substratehaving a stacked structure composed of a pad oxide layer and a siliconnitride layer; forming a liner oxide layer on a sidewall of the trench;and performing a nitrogen treatment to transfer the pad oxide layer intosilicon oxynitride layer.

It is another aspect of the present invention to provide a method offorming a shallow trench isolation. The present invention comprises thesteps of forming a trench on a substrate, wherein the substrate having astacked structure composed of a pad oxide layer and a silicon nitridelayer; forming a liner oxide layer on a sidewall of the trench;performing a nitrogen treatment to transfer the pad oxide layer intosilicon oxynitride layer; and forming a silicon oxide layer to fill thetrench.

It is another aspect of the present invention to provide a method offorming a shallow trench isolation. The present invention comprises thesteps of forming a pad oxide layer and a silicon nitride layersequentially on a semiconductor substrate; performing a nitrogentreatment to transfer the pad oxide layer into silicon oxynitride layer;performing a photolithographic step to form a trench on thesemiconductor substrate; forming a liner oxide layer on a sidewall ofthe trench; forming a silicon oxide layer to fill the trench; andperforming a polishing step.

As described above, the present invention discloses a method of formingthe shallow trench isolation by introducing a nitrogen treatment afterthe step of forming the trench so that the exposed pad oxide layerlocated on the upper portion of the trench is transferred into siliconoxynitride layer. Therefore, the method of the present invention avoidsthe formation of the bird's break and electric influence of the device.Accordingly, the scale down requirement of the future device issatisfied according to the method of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of thisinvention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

FIGS. 1 to 5 are schematic drawings, showing a conventional process offorming a shallow trench isolation; and

FIGS. 6 to 11 are schematic drawings, showing a method of forming ashallow trench isolation according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention provides a method of forming a shallow trenchisolation by introducing a nitrogen treatment after the etching step offorming the shallow trench isolation to nitrifying the exposed pad oxidelayer located on the upper edge of the shallow trench isolation and toprevent the bird's break from forming on the upper edge of the shallowtrench isolation.

Referring to FIGS. 6 through 11, showing a process of forming theshallow trench isolation structure according one preferred embodiment ofthe present invention. As shown in FIG. 6, a semiconductor substrate110, for example, a silicon substrate, is provided. A pad oxide layer112, for example, a silicon oxide layer, is then formed on thesemiconductor substrate 110 by heating in an oxygen-containingcondition. After that, a silicon nitride layer 114 is then deposited onthe pad oxide layer 112 by, for example, LPCVD or other depositionmethod. A photolithography process is then performed on the wafer.

Referring to FIG. 7, a layer of photoresist is then patterned to exposethe silicon nitride layer 114 after the forming step of the siliconnitride 114. A predetermined mask pattern is then transferred to thelayer of photoresist to form the photoresist layer 116. Thereafter, anetching process is then performed on the wafer.

Referring to FIG. 8, the formed photoresist layer 116 can be used as themask during the etching process. The underlying silicon nitride layer114, pad oxide layer 112 and substrate 110 are then etched sequentiallyby wet etching or dry etching, the present invention is not limitedthereto, to form a shallow trench 120 on the substrate 110.

Referring to FIG. 9, while the trench 120 has a predetermined depthduring the etching process, the photoresist layer 116 is then removed byashing. A nitrogen treatment is then performed to nitrify the exposedpad oxide layer 112 by, for example, furnace or RTA (Rapid ThermalAnneal) and to transfer the pad oxide layer into a silicon oxynitridelayer, wherein the preferred gas used in the nitrogen treatment is, forexample, N₂, NO, N₂O or NH₃. Thereafter, a liner oxide layer 118 is thenconformal formed on the surface of the etched trench 120. It is notedthat the gas applied in the present invention is not limited thereto,any gas suitable for the nitrogen treatment is also within the scope ofthe present invention.

Referring to FIG. 10, a silicon oxide layer 122 is then formed to fillthe trench 120 by, for example, CVD or other deposition method.Thereafter, a polishing process is then preformed on the wafer.

Referring to FIG. 11, a CMP process or other polishing method is thenapplied to remove the silicon nitride layer 114, silicon oxide layer122, and pad oxide layer 112. exceed the shallow trench 120, and leavethe layers located within the trench 20.

As described above, the present invention discloses a method of formingthe shallow trench isolation by introducing a nitrogen treatment afterthe step of forming the trench, so that the exposed pad oxide layerlocated on the upper portion of the trench is transferred into siliconoxynitride layer. Therefore, the method of the present invention avoidsthe formation of the bird's break and electric influence of the device.Accordingly, the scale down requirement of the future device issatisfied according to the method of the present invention.

As is understood by a person skilled in the art, the foregoing preferredembodiments of the present invention are illustrated of the presentinvention rather than limiting of the present invention. It is intendedto cover various modifications and similar arrangements included withinthe spirit and scope of the appended claims, the scope of which shouldbe accorded the broadest interpretation so as to encompass all suchmodifications and similar structure.

What is claimed is:
 1. A method of forming a shallow trench isolation,comprising: forming a trench on a substrate, wherein the substratehaving a stacked structure composed of a pad oxide layer and a siliconnitride layer formed thereon; transferring only a sidewall of the padoxide layer exposed to the trench into silicon oxynitride by a nitrogentreatment performed thereon; forming a liner oxide layer on a sidewallof the trench; and forming a silicon oxide layer to fill the trench. 2.The method of claim 1, wherein the step of forming the trench furthercomprises: forming the pad oxide layer, the silicon nitride layer, and aphotoresist layer in sequence; performing a photolithography and anetching step to form the trench; and removing the photoresist layer. 3.The method of claim 1, wherein the nitrogen treatment is performed in afurnace.
 4. The method of claim 3, wherein the nitrogen treatmentutilizes a gas selected from a group composed of N₂, NO, N₂O, and NH₃.5. The method of claim 1, wherein the nitrogen treatment comprises arapid thermal anneal step.
 6. The method of claim 5, wherein thenitrogen treatment utilizes a gas selected from a group composed of N₂,NO, N₂O, and NH₃.
 7. A method of forming a shallow trench isolation,comprising: forming a pad oxide layer and a silicon nitride layersequentially on a semiconductor substrate; performing aphotolithographic step to form a trench on the semiconductor substrate;transferring only a sidewall of the pad oxide layer exposed to thetrench into silicon oxynitride by a nitrogen treatment performedthereon; forming a liner oxide layer on a sidewall of the trench;forming a silicon oxide layer to fill the trench; and performing apolishing step.
 8. The method of claim 7, wherein the nitrogen treatmentis performed in a furnace.
 9. The method of claim 8, wherein thenitrogen treatment utilizes a gas selected from a group composed of N₂,NO, N₂O, and NH₃.
 10. The method of claim 7, wherein the nitrogentreatment comprises a rapid thermal anneal step.
 11. The method of claim10, wherein the nitrogen treatment utilize a gas selected from a groupcomposed of N₂, NO, N₂O, and NH₃.